Alif Semiconductor /AE512F80F5582LS_CM55_HE_View /ETH /ETH_MAC_CSR_SW_CTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as ETH_MAC_CSR_SW_CTRL

SEEN=Val_0x0, RCWE=Val_0x0

Description

CSR Software Control Register

Fields

RCWE	Register Clear on Write 1 Enable When this bit is set, the access mode of some register fields changes to Clear on Write 1, the application needs to set that respective bit to 1 to clear it. When this bit is reset, the access mode of these register fields remain as Clear on Read. 0 (Val_0x0): Register clear on write 1 is disabled 1 (Val_0x1): Register clear on write 1 is enabled
SEEN	Slave Error Response Enable When this bit is set, the MAC responds with Slave Error for accesses to reserved registers in CSR space. When this bit is reset, the MAC responds with OKAY response to any register accessed from CSR space. 0 (Val_0x0): Slave error response is disabled 1 (Val_0x1): Slave error response is enabled

Links

() ()